# Is it possible to simulate a RS latch?

Combining the solutions provided from the nice guys here to my previous two questions(first, second), Interesting enough, simulations for simple logic gates can be implemented easily. An example is given below. Is it possible to simulate logic gates involved loop-backs, such as RS Latchs or JK Flip-flops? I wonder.

(********* gates ************)
not[str : _String] :=
StringJoin[
Characters[str] /. {"1" -> False, "0" -> True} /. {False -> "0",
True -> "1"}];

nand[str : {__String}] :=
not[StringJoin[
Characters[str] /. {"0" -> False, "1" -> True}] /. {False ->
"0", True -> "1"}]];

(********* display ************)
funB[str : {__String}, opts : OptionsPattern[]] :=
Module[{fs, n, timd},
fs = Riffle[#, #]~Append~Last[#] & /@ ToExpression@Characters@str;
n = Length@First@fs;
timd = Reverse@fs~Append~PadLeft[{1}, n, {1, 0}];
ListLinePlot[MapIndexed[#1 + 2 First@#2 - 2 &, timd],
InterpolationOrder -> 0,
Frame -> True,
Epilog -> {Table[
Text[Style[ln, {12, Italic}], {ln*2 + .5, 2 *Length[str] }], {ln, 1, 8}],
Dashed, Lighter@Lighter@Blue,
Table[Line[{{ln, 0}, {ln, 2 *Length[str]}}], {ln, 1, 9*2, 2}]},
FrameTicks -> {Thread[{Range[1.5, n - 1.5, 2], Range[n/2]}],
Thread[{Range[0.5, 2 Length@timd, 2],
Join[Reverse@str, {"clock"}]}], None, None},
PlotRange -> {{0, n + 1}, Automatic}, opts]]

Dynamic[Refresh[str2 = StringRotateRight /@ str2;
funB[str2, ImageSize -> 400]  , UpdateInterval -> 0.5],
TrackedSymbols -> {}]

(********* testing ************)
inp1 = "11000000";
inp2 = "10000001";
str2 = {inp1, not[inp1], inp2,  nand[{not[inp1], inp2}]};


@Mr. Wizard Oh yes, it seems possible to build functions for the RS latch and JK flip-flop from their fundamental characteristics instead of just wiring the "logic gates" from strictly following their symbolic diagrams.

-
Including definitions of "RS Latchs" and "JK Flip-flops" would be helpful and relevant. –  Mr.Wizard Jul 21 at 6:45